1. Field of the Invention
The present invention relates to a semiconductor substrate and a fabrication method therefor, and in particular to a semiconductor substrate and a fabrication method therefor which are capable of avoiding the problems of a conventional SOI (Silicon On Insulator) substrate.
2. Description of the Conventional Art
Recently, an SOI (Silicon On Insulator) substrate structure which is known as the next generation semiconductor substrate, is increasingly used in order to reduce a parasitic effect of the substrate which occurs in conventional integrated circuits and to effectively separate devices and circuits from one another in an integrated circuit.
FIGS. 1A through 1C are cross-sectional views illustrating a conventional SOI substrate and a fabrication method thereof. As shown in FIG. 1A, an oxide layer 13 which acts as an insulation layer, is formed on a first silicon wafer 11 which is capable of having an integrated circuit formed thereon. As shown in FIG. 1B, a second silicon wafer 15 which is used as a base substrate, is mounted on the oxide layer 13 by a thermal bonding method, etc. Finally, as shown in FIG. 1C, the resultant structure is inverted, and an upper surface of the first silicon wafer 11 is polished to a predetermined thickness, thus forming an SOI structure substrate.
Generally, when forming an oxide layer on a silicon layer under a high temperature environment, various electric charges are formed on the surface of the silicon layer. Therefore, when the oxide layer 13 is formed on the first silicon wafer 11 under a high temperature environment, various electric charges are formed on the surface of the first silicon wafer 11 or within the oxide layer 13. In addition, fixed electric charges are formed within the oxide layer 13 to a depth of about 35 .ANG. from the surface of the first silicon wafer 11, and these electric charges which are positive electric charges are not mobile under an applied external field, differently from other electric charges. A negative depletion charge is formed in the first silicon wafer 11 in which the devices are to be integrated by the positive fixed electric charges. The region in which the depletion electric charges are formed affects the breakdown voltage characteristic of a device. Namely, since the depletion electric charge region is previously formed before electrical power is externally supplied to the integrated circuit, when the electrical power is actually supplied thereto, the breakdown voltage of the device drops, which is undesirable when implementing a device which requires a high breakdown voltage.
Therefore, when fabricating an SOI substrate as shown in FIG. 1C and forming an oxide layer on the silicon substrate, the oxide layer is formed such that the density of the fixed electric charges formed on the surface of the oxide layer is controlled within a density (about 10.sup.10 cm.sup.-2) which does not affect the threshold voltage of the device. However, a problem occurs when the density of the fixed electric charges is formed identically in the junction surface during the joining under a high temperature environment, or when the density of the electric charge below the density (about 10.sup.10 cm.sup.-2) therein is formed. Currently, the above-described problems have not been resolved. Namely, the density of the fixed electric charge formed at the boundary surface between the first silicon wafer 11 and the oxide layer 13 formed thereon can be controlled below about 10.sup.10 cm.sup.-2, by controlling the growing condition of the oxide layer 13. However, since the density of the fixed charge formed at the boundary surface between the oxide layer 13 and the second silicon wafer 15 which are bonded at a high temperature is 10.sup.11 cm.sup.-2 at maximum, the depletion layer is formed before a voltage is supplied to the first silicon wafer 11, so that a parasitic phenomenon occurs in the devices of the integrated circuit.